Abstract / Summary
Continuous electrocardiogram (ECG) monitoring in wearable biomedical devices requires processing architectures that balance computational simplicity with hardware efficiency. This paper presents a compact, silicon-proven System-on-Chip (SoC) integrating a PicoRV32 (RV32I) RISC-V processor core with a dedicated multiplierless 1D convolution accelerator for real-time binary ECG anomaly detection. The accelerator implements a hard-wired three-tap Laplacian kernel ([−1,2,−1]) coupled with a programmable threshold comparator. By replacing hardware multipliers with a shift-add-negate tree, the datapath requires O(N) full-adder equivalents for N-bit samples, compared with O(N2) for a multiplier-based 3-tap filter, and executes deterministically in a single clock cycle. The accelerator interfaces with the RISC-V core through a memory-mapped handshake bus. Fabricated in a 180-nm CMOS process, the SoC occupies an active core area of 0.936 mm2 (9373 standard-cell instances at 75.2% density) and was validated on a custom PCB using a UART host interface streaming MIT-BIH Arrhythmia Database records. On five records (10,393 beats) with per-patient threshold calibration, the chip achieves 95.88% Normal/Abnormal accuracy. At 1.8 V and 100 MHz the measured active power is 25.2 mW, and the measured sleep-mode leakage is 44 nW (44 nA at 1.0 V). These results provide a compact, area-efficient ASIC platform for wearable cardiac monitoring, whose power consumption can be further reduced by operating at lower clock frequencies.